1. Field of the Invention
The present invention relates to an integrated circuit package, and more particularly to a stacked integrated circuit package having a package-on-package structure and a method for manufacturing the same.
2. Description of the Related Art
In the semiconductor industry, a product having light weight, compact size, multi-functionality and high performance is generally demanded. One technology necessary to meet such demand is integrated circuit packaging.
Integrated circuit packaging is a technology of forming input/output signal terminals to a main board using a lead frame or a printed circuit board and molding the terminals with a encapsulant to protect a semiconductor chip such as a single device and an integrated circuit, formed by stacking electric circuits and wires, from various external environmental factors such as dust, moisture, and electric and mechanical loads and to optimize or maximize electrical performance of the semiconductor chip.
As products having integrated circuit packages mounted therein have recently been made lightweight and slim and provided with compact side, and many functions are demanded of the products, System in Package (SIP) and Package on Package (POP) technologies, which allow a plurality of semiconductor chips to be mounted on an integrated circuit package, have entered into widespread use as integrated circuit packaging technology.
The number of I/O terminals increases with increase in capacity of an integrated circuit package. To increase the number of I/O terminals without causing increase of the entire size of the integrated circuit package, forming a through mold via (TMV) by providing a through hole to a mold portion and filling the through hole with conductive paste has been proposed.
FIGS. 1A to 1E are cross-sectional views illustrating the processes of manufacturing a conventional TMV-type stacked integrated circuit package. The method for manufacturing the conventional TMV-type stacked integrated circuit package is described below with reference to FIGS. 1A to 1E.
As shown in FIG. 1A, a substrate 10 provided with wire terminals 11, external terminals 12 and via contacts 13 electrically connecting the wire terminals 11 and the external terminals 12 is first prepared.
Next, as shown in FIG. 1B, the semiconductor chip 20 and solder balls 30 are attached to the substrate 10. At this time, the semiconductor chip 20 is connected to the wire terminals 11 on the substrate 10 via conductive bumps 22 in a flip chip bonding manner, with the circuit pattern 21 of the semiconductor chip 20 facing downward. In addition, the solder balls 30 are formed at the edge of the substrate 10.
Next, as shown in FIG. 1C, the space between the semiconductor chip 20 and the substrate 10 is filled with an underfill 41. Then, molding is performed on the entire upper surfaces of the semiconductor chip 20 and the substrate 10 using the encapsulant to form a molding portion 40.
Next, as shown in FIG. 1D, the molding portion 40 is subjected to etching through laser machining to form a via hole 50 such that a part of the solder ball 30 on the upper surface of the substrate 10 is exposed.
Next, as shown in FIG. 1E, an upper integrated circuit package 60 is stacked on the lower integrated circuit package which is formed through the processes shown in FIGS. 1A to 1D, and then solder balls are formed on the bottom surface of the substrate 10.
However, in the case on the conventional TMV-type stacked integrated circuit package described above, laser machining process for formation of a via hole takes a long time, and the number of I/O terminals is limited. Further, rewiring on the upper integrated circuit package is substantially impossible. Thereby, circuit design for the conventional TMV-type stacked integrated circuit package is difficult.
However, with increased demand for slim and lightweight design and simplicity of electronic appliances, efforts are continuously put forth to further reduce thickness and weight of an integrated circuit package.